processor - ARM modes and why are there so many? -

I am currently reading / learning about ARM architecture ... and I was thinking that so many Why are the methods (FIQ, user, system, supervisor, IRQ, ...).

My question is why do we need so many ways? What users and systems will not be sufficient?

Thanks in advance. This is just an architectural decision, the biggest advantage of many methods is that they have some bank registers. With those additional registrars, you can write less complex exception ratios too .

If you choose only two, then the USR and SAS are probably good as any option, but what will happen if you take exception? Normal ARM model is to go into exception mode, after the exception of the exception of the bank linked register, to which you want to return after solving the exception, in the exception mode, the processor position in the SPSR register Set to save and then jump on the exception vector, USR and SES share all their registers - using this model, every time you take an interval, then come Will blow out your function returns (LR)!

Especially in FIQ mode there is more than banking registers. Other exception modes are with those "F" part of the Additional Registrar FIQ - this is for "Fast". The more processor in the software will speed up your interrupt handler to save and restore the context.